Field effect transistor and method of its manufacture

ABSTRACT

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to field effect transistors, inparticular trench DMOS transistors, and methods of their manufacture.

[0002] Power field effect transistors, e.g., MOSFETs (metal oxidesemiconductor field effect transistors), are well known in thesemiconductor industry. One type of MOSFET is a DMOS (double diffusedmetal oxide semiconductor) transistor. DMOS transistors typicallyinclude a substrate on which an epitaxial layer is grown, a doped sourcejunction, a doped heavy body, a doped well of the same (p or n) dopingas the heavy body, and a gate electrode. In trenched DMOS transistorsthe gate electrode is a vertical trench. The heavy body is typicallydiffused deeper than the bottom of the trench, to minimize electricfield at the bottom corners of the trench and thereby prevent avalanchebreakdown from damaging the device. The trench is filled with conductivepolysilicon, and the polysilicon is generally overetched, to assure thatit is completely removed from the surface surrounding the trench. Thisoveretching generally leaves a recess between the top of the polysiliconand the surface of the semiconductor substrate (i.e., the surface of theepitaxial layer). The depth of this recess must be carefully controlledso that it is shallower than the depth of the source junctions. If therecess is deeper than the source junctions the source may miss the gate,resulting in high on-state resistance, high threshold, and potentially anon-functional transistor.

[0003] The source and drain junctions can be doped with either p-type orn-type dopants; in either case, the body will be doped with the oppositedopant, e.g., for n-type source and drain the body will be p-type. DMOStransistors in which the source and drain are doped with p-type carriersare referred to as “p-channel”. In p-channel DMOS transistors a negativevoltage applied to the transistor gate causes current flow from thesource region, through a channel region of the body, an accumulationregion of the epitaxial layer, and the substrate, to the drain region.Conversely, DMOS transistors, in which the source and drain are dopedwith n-type carriers, are referred to as “n-channel”. In n-channel DMOStransistors a positive voltage applied to the transistor gate causescurrent to flow from drain to source.

[0004] It is desirable that DMOS transistors have low source to drainresistance (Rds_(on)) when turned on and low parasitic capacitance. Thetransistor structure should also avoid “punchthrough”. Punchthroughoccurs when, upon application of a high drain to source voltage,depletion into the body region extends to the source region, forming anundesirable conductive path through the body region when the transistorshould be off. Finally, the transistor should have good “ruggedness”,i.e., a high activation current is needed to turn on the parasitictransistor that inherently exists in DMOS transistors.

[0005] Generally a large number of MOSFET cells are connected inparallel forming a single transistor. The cells may be arranged in a“closed cell” configuration, in which the trenches are laid out in agrid pattern and the cells are enclosed on all sides by trench walls.Alternatively, the cells may be arranged in an “open cell”configuration, in which the trenches are laid out in a “stripe” patternand the cells are only enclosed on two sides by trench walls. Electricfield termination techniques are used to terminate junctions (dopedregions) at the periphery (edges) of the silicon die on which thetransistors are formed. This tends to cause the breakdown voltage to behigher than it would otherwise be if controlled only by the features ofthe active transistor cells in the central portions of the die.

SUMMARY OF THE INVENTION

[0006] The present invention provides field effect transistors that havean open cell layout that provides good uniformity and high cell densityand that is readily scalable. Preferred trenched DMOS transistorsexhibit low Rds_(on), low parasitic capacitance, excellent reliability,resistance to avalanche breakdown degradation, and ruggedness. Preferreddevices also include a field termination that enhances resistance toavalanche breakdown. The invention also features a method of makingtrench DMOS transistors.

[0007] In one aspect, the invention features a trenched field effecttransistor that includes

[0008] (a) a semiconductor substrate, (b) a trench extending apredetermined depth into the semiconductor substrate, (c) a pair ofdoped source junctions, positioned on opposite sides of the trench, (d)a doped heavy body positioned adjacent each source junction on theopposite side of the source junction from the trench, the deepestportion of the heavy body extending less deeply into said semiconductorsubstrate than the predetermined depth of the trench, and (e) a dopedwell surrounding the heavy body beneath the heavy body.

[0009] Preferred embodiments include one or more of the followingfeatures. The doped well has a substantially flat bottom. The depth ofthe heavy body region relative to the depths of the well and the trenchis selected so that the peak electric field, when voltage is applied tothe transistor, will be spaced from the trench. The doped well has adepth less than the predetermined depth of the trench. The trench hasrounded top and bottom corners. There is an abrupt junction at theinterface between the heavy body and the well, to cause the peakelectric field, when voltage is applied to the transistor, to occur inthe area of the interface.

[0010] In another aspect, the invention features an array of transistorcells. The array includes (a) a semiconductor substrate, (b) a pluralityof gate-forming trenches arranged substantially parallel to each otherand extending in a first direction, the space between adjacent trenchesdefining a contact area, each trench extending a predetermined depthinto said substrate, the predetermined depth being substantially thesame for all of said gate-forming trenches; (c) surrounding each trench,a pair of doped source junctions, positioned on opposite sides of thetrench and extending along the length of the trench, (d) positionedbetween each pair of gate-forming trenches, a doped heavy bodypositioned adjacent each source junction, the deepest portion of eachsaid heavy body extending less deeply into said semiconductor substratethan said predetermined depth of said trenches, (e) a doped wellsurrounding each heavy body beneath the heavy body; and (f) p+ and n+contacts disposed at the surface of the semiconductor substrate andarranged in alternation along the length of the contact area.

[0011] Preferred embodiments include one or more of the followingfeatures. The doped well has a substantially flat bottom. The depth ofeach heavy body region relative to the depths of the wells and thegate-forming trenches is selected so that the peak electric field, whenvoltage is applied to the transistor, will be spaced from the trench.The doped wells have a depth less than the predetermined depth of thetrenches. The trenches have rounded top and bottom corners. There is anabrupt junction at the interface between each heavy body and thecorresponding well, to cause the peak electric field, when voltage isapplied to the transistor, to occur in the area of the interface. Thearray also includes a field termination structure surrounding theperiphery of the array. The field termination structure includes a wellhaving a depth greater than that of the gate-forming trenches. The fieldtermination structure includes a termination trench extendingcontinuously around the periphery of the array, more preferably aplurality of concentrically arranged termination trenches.

[0012] In yet another aspect, the invention features a semiconductor diethat includes (a) a plurality of DMOS transistor cells arranged in anarray on a semiconductor substrate, each DMOS transistor cell includinga gate-forming trench, each of said gate-forming trenches having apredetermined depth, the depth of all of the gate-forming trenches beingsubstantially the same; and (b) surrounding the periphery of the array,a field termination structure that extends into the semiconductorsubstrate to a depth that is deeper than said predetermined depth ofsaid gate-forming trenches.

[0013] Preferred embodiments include one or more of the followingfeatures. The field termination structure includes a doped well. Thefield termination structure includes a termination trench. The fieldtermination structure includes a plurality of concentrically arrangedtermination trenches. Each of the DMOS transistor cells furthercomprises a doped heavy body and the doped heavy body extends into thesemiconductor substrate to a depth than is less than the predetermineddepth of the gate-forming trenches.

[0014] The invention also features a method of making a heavy bodystructure for a trenched DMOS transistor including (a) providing asemiconductor substrate; (b) implanting into a region of the substrate afirst dopant at a first energy and dosage; and (c) subsequentlyimplanting into said region a second dopant at a second energy anddosage, said second energy and dosage being relatively less than saidfirst energy and dosage.

[0015] Preferred embodiments include one or more of the followingfeatures. The first and second dopants both comprise boron. The firstenergy is from about 150 to 200 keV. The first dosage is from about 1E15to 5E15. The second energy is from about 20 to 40 keV. The second dosageis from about 1E14 to 1E15.

[0016] Additionally, the invention features a method of making a sourcefor a trenched DMOS transistor including (a) providing a semiconductorsubstrate; (b) implanting into a region of the substrate a first dopantat a first energy and dosage; and (c) subsequently implanting into theregion a second dopant at a second energy and dosage, the second energyand dosage being relatively less than the first energy and dosage.

[0017] Preferred embodiments include one or more of the followingfeatures. The first dopant comprises arsenic and the second dopantcomprises phosphorus. The first energy is from about 80 to 120 keV. Thefirst dosage is from about 5E15 to 1E16. The second energy is from about40 to 70 keV. The second dosage is from about 1E15 to 5E15. Theresulting depth of the source is from about 0.4 to 0.8 μm in thefinished DMOS transistor.

[0018] In another aspect, the invention features a method ofmanufacturing a trenched field effect transistor. The method includes(a) forming a field termination junction around the perimeter of asemiconductor substrate, (b) forming an epitaxial layer on thesemiconductor substrate, (c) patterning and etching a plurality oftrenches into the epitaxial layer; (d) depositing polysilicon to fillthe trenches, (e) doping the polysilicon with a dopant of a first type,(f) patterning the substrate and implanting a dopant of a second,opposite type to form a plurality of wells interposed between adjacenttrenches, (g) patterning the substrate and implanting a dopant of thesecond type to form a plurality of second dopant type contact areas anda plurality of heavy bodies positioned above the wells, each heavy bodyhaving an abrupt junction with the corresponding well, (h) patterningthe substrate and implanting a dopant of the first type to providesource regions and first dopant type contact areas; and (i) applying adielectric to the surface of the semiconductor substrate and patterningthe dielectric to expose electrical contact areas.

[0019] Other features and advantages of the invention will be apparentfrom the following detailed description, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a highly enlarged, schematic perspective cross-sectionalview showing a portion of a cell array including a plurality of DMOStransistors according to one aspect of the invention. The source metallayer and a portion of the dielectric layer have been omitted to showthe underlying layers. FIGS. 1a and 1 b are side cross-sectional viewsof a single line of transistors from the array of FIG. 1, taken alonglines A-A and B-B, respectively. In FIGS. 1a and 1 b the source metaland dielectric layers are shown.

[0021]FIG. 2 is a highly enlarged schematic side cross-sectional view ofa semiconductor die showing a portion of the cell array and the fieldtermination.

[0022]FIG. 3 is a flow diagram showing the photo mask sequence of apreferred process for forming a trench DMOS transistor of FIG. 1.

[0023] FIGS. 4-4 k are schematic side cross-sectional views showing theindividual steps of the process diagrammed in FIG. 3. The figure numbersfor the detailed views in FIGS. 4-4 k are shown parenthetically underthe corresponding diagram boxes in FIG. 3.

[0024]FIGS. 5 and 5b are spreading resistance profile graphs, reflectingthe dopant concentration distribution at different regions of thetransistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] A cell array 10, including a plurality of rows 12 of trenchedDMOS transistors, is shown in FIG. 1. Cell array 10 has an open cellconfiguration, i.e., trenches 14 run in only one direction, rather thanforming a grid. Individual cells are formed by alternating n+ sourcecontacts 16 and p+ contacts 18 in rows 20 that run parallel to andbetween trenches 14. The configuration of the regions of each row thathave an n+ source contact are shown in cross-section in FIG. 1a, whilethe regions that have a p+ contact are shown in FIG. 1b.

[0026] As shown in FIGS. 1a and 1 b, each trenched DMOS transistorincludes a doped n+ substrate (drain) layer 22, a more lightly doped n−epitaxial layer 24, and a gate electrode 28. Gate electrode 28 comprisesa conductive polysilicon that fills a trench 14. A gate oxide 26 coatsthe walls of the trench and underlies the polysilicon. The top surfaceof the polysilicon is recessed from the surface 30 of the semiconductorsubstrate by a distance R (typically from about 0 to 0.4 μm). N+ dopedsource regions 32 a, 32 b are positioned one on each side of the trench14. A dielectric layer 35 covers the trench opening and the two sourceregions 32 a, 32 b. Extending between the source regions of adjacentcells is a p+ heavy body region 34 and, beneath it, a flat-bottomed p−well 36. In the areas of the cell array which have a n+ contact 16, ashallow n+ doped contact region extends between the n+ source regions. Asource metal layer 38 covers the surface of the cell array.

[0027] The transistor shown in FIGS. 1a and 1 b includes severalfeatures that enhance the ruggedness of the transistor and itsresistance to avalanche breakdown degradation.

[0028] First, the depth of the p+ heavy body region 34 relative to thedepths of the trench 14 and the flat bottom of the p− well is selectedso that the peak electric field when voltage is applied to thetransistor will be approximately halfway between adjacent trenches. Thepreferred relative depths of the p+ heavy body, the p− well and thetrench are different for different device layouts. However, preferredrelative depths can be readily determined empirically (by observing thelocation of peak electric field) or by finite element analysis.

[0029] Second, the bottom corners of the trench 14 are rounded(preferably, the top corners are also rounded; this feature is notshown). Corner rounding can be achieved using the process described incopending application U.S. Ser. No. ______ filed on Oct. 28, 1997. Therounded corners of the trench also tend to cause the peak electric fieldto be moved away from the trench corners and towards a central locationbetween adjacent trenches.

[0030] Third, an abrupt junction at the interface between the p+ heavybody and the p− well causes the peak electric field to occur in thatarea of the interface. Avalanche multiplication initiates at thelocation of the peak electric field, thus steering hot carriers awayfrom the sensitive gate oxide and channel regions. As a result, thisstructure improves reliability and avalanche ruggedness withoutsacrificing cell density as much as a deeper heavy body junction. Thisabrupt junction can be achieved by the double doping process that willbe described below, or by other processes for forming abrupt junctions,many of which are known in the semiconductor field.

[0031] Lastly, referring to FIG. 2, the cell array is surrounded by afield termination junction 40 which increases the breakdown voltage ofthe device and draws avalanche current away from the cell array to theperiphery of the die. Field termination junction 40 is a deep p+ well,preferably from about 1 to 3 μm deep at its deepest point, that isdeeper than the p+ heavy body regions 34 in order to reduce the electricfield caused by the junction curvature. A preferred process for makingthe above-described transistors is shown as a flow diagram in FIG. 3,and the individual steps are shown schematically in FIGS. 4-4 k. It isnoted that some steps that are conventional or do not requireillustration are described below but not shown in FIGS. 4-4 k. Asindicated by the arrows in FIG. 3, and as will be discussed below, theorder of the steps shown in FIGS. 4-4 k can be varied. Moreover, some ofthe steps shown in FIGS. 4-4 k are optional, as will be discussed.

[0032] A semiconductor substrate is initially provided. Preferably, thesubstrate is a N++ Si substrate, having a standard thickness, e.g., 500μm, and a very low resistivity, e.g., 0.001 to 0.005 Ohm-cm. Anepitaxial layer is deposited onto this substrate, as is well known,preferably to a thickness of from about 4 to 10 μm. Preferably theresistivity of the epitaxial layer is from about 0.1 to 3.0 Ohm-cm.

[0033] Next, the field termination junction 40 is formed by the stepsshown in FIGS. 4-4 c. In FIG. 4, an oxide layer is formed on the surfaceof the epitaxial layer. Preferably, the thickness of the oxide is fromabout 5 to 10 kÅ. Next, as shown in FIG. 4a, the oxide layer ispatterned and etched to define a mask, and the p+ dopant is introducedto form the deep p+ well field termination. A suitable dopant is boron,implanted at an energy of from about 40 to 100 keV and a dose of 1E14(1×10¹⁴) to 1E16 cm⁻². As shown in FIG. 4b, the p+ dopant is then drivenfurther into the substrate, e.g., by diffusion, and a field oxide layeris formed over the p+ junction. Preferably the oxide thickness is fromabout 4 to 10 kÅ.

[0034] Finally, the oxide (FIG. 4) over the active area of the substrate(the area where the cell array will be formed) is patterned and removedby any suitable etching process, leaving only the field oxide insuitable areas. This leaves the substrate ready for the following stepsthat will form the cell array.

[0035] It is noted that, as an alternative to steps 4-4 c, a suitablefield termination structure can be formed using a ring-shaped trenchwhich surrounds the periphery of the cell array and acts to lessen theelectric field and increase the resistance to avalanche breakdowndegradation. This trench field termination does not require a fieldoxide or deep p+ body junction to be effective. Consequently, it can beused to reduce the number of process steps. Using a trench ring (ormultiple concentric trench rings) to form a field termination isdescribed in, e.g., U.S. Pat. No. 5,430,324, the full disclosure ofwhich is hereby incorporated herein by reference. Preferably, the trenchwould have substantially the same depth as the trenches in the cellarray.

[0036] The cell array is formed by the steps shown in FIGS. 4d-4 k.First, a plurality of trenches are patterned and etched into theepitaxial layer of the substrate (FIG. 4d). Preferably, as noted above,the trenches are formed using the process described in copendingapplication U.S. Ser. No. ______, so that the upper and lower corners ofeach trench will be smoothly rounded. As shown in FIG. 1 and describedabove, the trenches are patterned to run in only one direction, definedas an open cell structure. After trench formation, a gate oxide layer isformed on the trench walls, as is well known in the semiconductor field.Preferably the gate oxide has a thickness of from about 100 to 800Å.

[0037] Next, as shown in FIG. 4e, polysilicon is deposited to fill thetrench and cover the surface of the substrate, generally to a thicknessof from about 1 to 2 μm depending on the trench width (shown by thedotted lines in FIG. 4e). This layer is then planarized by the nature ofits thickness relative to the trench width, typically from about 2 to 5kÅ (indicated by solid lines in FIG. 4e). The polysilicon is then dopedto n-type, e.g., by conventional POCL₃ doping or by phosphorus implant.The backside of the wafer need not be stripped (as is conventionallydone prior to doping the polysilicon to enhance defect gettering)because any further doping of the highly doped substrate would beunlikely to result in any enhancement in defect gettering.

[0038] The polysilicon is then patterned with a photoresist mask andetched to remove it from the trench areas, as shown in FIG. 4f. A smallrecess between the top of the polysilicon in the trench and thesubstrate surface inherently results when the polysilicon is etchedcompletely to remove all of the polysilicon from the substrate surface.The depth of this recess must be controlled so that it does not exceedthe depth of the n+ source junction that will be formed in a later step.To reduce the need to carefully control this aspect of the process, arelatively deep n+ source junction is formed, as will be discussedbelow.

[0039] Then, as shown in FIG. 4g, the p− well is formed by implantingthe dopant, e.g., a boron implant at an energy of 30 to 100 keV and adosage of 1E13 to 1E15, and driving it in to a depth of from about 1 to3 μm using conventional drive in techniques.

[0040] The next two steps (p+ heavy body formation) can be performedeither before formation of the n+ source junction, or afterwards, asindicated by the arrows in FIG. 3. P+ heavy body formation and n+ sourcejunction formation can be performed in either order because they areboth resist-masked steps and because there is no diffusion step inbetween. This advantageously allows significant process flexibility. Thep+ heavy body formation steps will be described below as being performedprior to source formation; it will be understood that n+ sourceformation could be performed first simply by changing the order of thesteps discussed below.

[0041] First, a mask is formed over the areas that will not be doped top+, as shown in FIG. 4h. (It is noted that this masking step is notrequired if the p+ heavy body is formed later, after the dielectriclayer has been applied and patterned for contact holes. (see FIG. 4k,below) so that the dielectric itself provides a mask.) As discussedabove, it is preferred that the junction at the interface between the p−well and the p+ heavy body be abrupt. To accomplish this, a doubleimplant of dopant (e.g., boron) is performed. For example, a preferreddouble implant is a first boron implant at an energy of 150 to 200 keVand a dose of 1E15 to 5E15, and a second boron implant at an energy of20 to 40 keV and a dose of 1E14 to 1E15. The high energy first implantbrings the p+ heavy body as deep as possible into the substrate, so thatit will not compensate the n+ source junction to be introduced later.The second, lower energy/lower dose implant extends the p+ heavy bodyfrom the deep region formed during the first implant up to the substratesurface to provide the p+ contact 18. The resulting p+ heavy bodyjunction is preferably about 0.4 to 1 μm deep at this stage of theprocess (final junction depth after drive-in is preferably about 0.5 to1.5 μm deep), and includes a region of high dopant concentration nearthe interface with the p− well, and a region of relatively low dopantconcentration at the contact surface of the p+ heavy body. A preferredconcentration distribution is shown in FIG. 5.

[0042] It will be appreciated by those skilled in the art that theabrupt junction can be formed in many other ways, e.g., by diffuseddopants, by using a continuous dopant source at the surface or by usingatoms that diffuse slowly.

[0043] After the formation of the p+ heavy body, a conventional resiststrip process is performed to remove the mask, and a new mask ispatterned to prepare the substrate for the formation of the n+ sourcejunction. This mask is a n+ blocking mask and is patterned to cover theareas of the substrate surface which are to provide p+ contacts 18(FIGS. 1 and 1b), as shown in FIG. 4i. This results in the formation ofalternating p+ and n+ contacts after n-type doping (see lines A-A andB-B and cross-sectional views A-A and B-B in FIG. 41, which correspondto FIGS. 1a and 1 b).

[0044] The n+ source regions and n+ contact are then formed using adouble implant. For example, a preferred double implant process is afirst implant of arsenic at an energy of 80 to 120 keV and a dose of5E15 to 1E16 followed by a second implant of phosphorus at an energy of40 to 70 keV and a dose of 1E15 to 5E15. The phosphorus implant forms arelatively deep n+ source junction, which allows more processflexibility in the depth of the polysilicon recess, as discussed above.Phosphorus ions will penetrate deeper into the substrate during implantand also during later diffusion steps. Advantageously, the n+ sourceregions will have a depth of about 0.4 to 0.8 μm after diffusion. Thearsenic implant extends the n+ source to the substrate surface, and alsoforms the n+ contacts 16 (see FIGS. 1 and 1a) by compensating(converting) the p-type surface of the p+ heavy body to n-type in thedesired contact area. The preferred sheet resistance profiles for the n+source along the edge of the trench, and the n+ contact are shown inFIGS. 5a and 5 b, respectively.

[0045] Thus, the alternating p+ and n+ contacts 18, 16, shown in FIG. 1are formed by patterning the substrate with appropriate masks and dopingwith the first p+ implant and the second n+ implant, respectively, asdescribed above. This manner of forming the alternating contactsadvantageously allows an open cell array having a smaller cell pitchthan is typical for such arrays and thus a higher cell density and lowerRds_(on).

[0046] Next, a conventional n+ drive is performed to activate thedopants. A short cycle is used, preferably 10 min at 900° C., so thatactivation occurs without excessive diffusion.

[0047] A dielectric material, e.g., borophosphate silicate glass (BPSG),is then deposited over the entire substrate surface and flowed in aconventional manner (FIG. 4j), after which the dielectric is patternedand etched (FIG. 4k) to define electrical contact openings over the n+and p+ contacts 16, 18.

[0048] As noted above, the p+ heavy body implant steps can be performedat this point, if desired (rather than prior to n+ source formation),eliminating the need for a mask and thus reducing cost and process time.

[0049] Next, the dielectric is reflowed in an inert gas, e.g., anitrogen purge. If the p+ body has been implanted immediately prior,this step is required to activate the p+ dopant. If the p+ body wasimplanted earlier, prior to the n+ drive, this step can be omitted ifthe dielectric surface is sufficiently smooth-edged around the contactopenings.

[0050] The cell array is then completed by conventional metalization,passivation deposition and alloy steps, as is well know in thesemiconductor field.

[0051] Other embodiments are within the claims. For example, while thedescription above is of an n-channel transistor, the processes of theinvention could also be used to form a p-channel transistor. Toaccomplish this, “p” and “n” would simply be reversed in the abovedescription, i.e., where “p” doping is specified above the region wouldbe “n” doped instead, and vice versa.

What is claimed is:
 1. A trenched field effect transistor comprising: asemiconductor substrate; a trench extending a predetermined depth intosaid semiconductor substrate; a pair of doped source junctions,positioned on opposite sides of the trench; a doped heavy bodypositioned adjacent each source junction on the opposite side of thesource junction from the trench, the deepest portion of said heavy bodyextending less deeply into said semiconductor substrate than saidpredetermined depth of said trench; and a doped well surrounding theheavy body beneath the heavy body.
 2. The trenched field effecttransistor of claim 1 wherein said doped well has a substantially flatbottom.
 3. The trenched field effect transistor of claim 1 wherein thedepth of the heavy body region relative to the depths of the well andthe trench is selected so that the peak electric field when voltage isapplied to the transistor will be spaced from the trench.
 4. Thetrenched field effect transistor of claim 1 wherein said doped well hasa depth less than the predetermined depth of said trench.
 5. Thetrenched field effect transistor of claim 1 wherein said trench hasrounded top and bottom corners.
 6. The trenched field effect transistorof claim 1 wherein there is an abrupt junction at the interface betweenthe heavy body and the well, to cause the peak electric field whenvoltage is applied to the transistor to occur in the area of theinterface.
 7. The trenched field effect transistor of claim 6 whereinsaid abrupt junction has a sheet resistance profile substantially asshown in FIG.
 5. 8. An array of transistor cells comprising: asemiconductor substrate; a plurality of gate-forming trenches arrangedsubstantially parallel to each other and extending in a first direction,the space between adjacent trenches defining a contact area, each trenchextending a predetermined depth into said substrate, the predetermineddepth being substantially the same for all of said gate-formingtrenches; surrounding each trench, a pair of doped source junctions,positioned on opposite sides of the trench and extending along thelength of the trench; positioned between each pair of gate-formingtrenches, a doped heavy body positioned adjacent each source junction,the deepest portion of each said heavy body extending less deeply intosaid semiconductor substrate than said predetermined depth of saidtrenches; a doped well surrounding each heavy body beneath the heavybody; and p+ and n+ contacts disposed at the surface of thesemiconductor substrate and arranged in alternation along the length ofthe contact area.
 9. The array of transistor cells of claim 8, whereineach said doped well has a substantially flat bottom.
 10. The array oftransistor cells of claim 8 wherein the depth of each heavy body regionrelative to the depths of the wells and the gate-forming trenches isselected so that the peak electric field when voltage is applied to thetransistor will occur approximately halfway between adjacentgate-forming trenches.
 11. The array of transistor cells of claim 8wherein each said doped well has a depth less than the predetermineddepth of said gate-forming trenches.
 12. The array of transistor cellsof claim 8 wherein each said gate-forming trench has rounded top andbottom corners.
 13. The array of transistor cells of claim 8 whereinthere is an abrupt junction at each interface between the heavy body andthe well, to cause the peak electric field when voltage is applied tothe transistor to occur in the area of the interface.
 14. The array oftransistor cells of claim 8 further comprising a field terminationstructure surrounding the periphery of the array.
 15. The array oftransistor cells of claim 14 wherein said field termination structurecomprises a well having a depth greater than that of the gate-formingtrenches.
 16. The array of transistor cells of claim 14 wherein saidfield termination structure comprises a termination trench extendingcontinuously around the periphery of the array.
 17. The array oftransistor cells of claim 16 wherein said field termination structurecomprises a plurality of concentrically arranged termination trenches.18. A semiconductor die comprising: a plurality of DMOS transistor cellsarranged in an array on a semiconductor substrate, each DMOS transistorcell including a gate-forming trench, each of said gate-forming trencheshaving a predetermined depth, the depth of all of the gate-formingtrenches being substantially the same; and surrounding the periphery ofthe array, a field termination structure that extends into thesemiconductor substrate to a depth that is deeper than saidpredetermined depth of said gate-forming trenches.
 19. The semiconductordie of claim 18 wherein said field termination structure comprises adoped well.
 20. The semiconductor die of claim 18 wherein said fieldtermination structure comprises a termination trench.
 21. Thesemiconductor die of claim 20 wherein said field termination structurecomprises a plurality of concentrically arranged termination trenches.22. The semiconductor die of claim 18 wherein each of said DMOStransistor cells further comprises a doped heavy body and said dopedheavy body extends into said semiconductor substrate to a depth that isless than the predetermined depth of said gate-forming trenches.
 23. Amethod of making a heavy body structure for a trenched DMOS transistorcomprising: providing a semiconductor substrate; implanting into aregion of the substrate a first dopant at a first energy and dosage; andsubsequently implanting into said region a second dopant at a secondenergy and dosage, said second energy and dosage being relatively lessthan said first energy and dosage.
 24. The method of claim 23 whereinsaid first and second dopants both comprise boron.
 25. The method ofclaim 23 wherein said first energy is from about 150 to 200 keV.
 26. Themethod of claim 25 wherein said first dosage is from about 1E15 to 5E15.27. The method of claim 23 wherein said second energy is from about 20to 40 keV.
 28. The method of claim 27 wherein said second dosage is fromabout 1E14 to 1E15.
 29. A method of making a source for a trenched DMOStransistor comprising: providing a semiconductor substrate; implantinginto a region of the substrate a first dopant at a first energy anddosage; and subsequently implanting into said region a second dopant ata second energy and dosage, said second energy and dosage beingrelatively less than said first energy and dosage.
 30. The method ofclaim 29 wherein said first dopant comprises arsenic and said seconddopant comprises phosphorus.
 31. The method of claim 29 wherein saidfirst energy is from about 80 to 120 keV.
 32. The method of claim 29wherein said first dosage is from about 5E15 to 1E16.
 33. The method ofclaim 29 wherein said second energy is from about 40 to 70 keV.
 34. Themethod of claim 33 wherein said second dosage is from about 1E15 to5E15.
 35. The method of claim 29 wherein the resulting depth of saidsource is from about 0.4 to 0.8 μm in the finished DMOS transistor. 36.A method of manufacturing a trenched field effect transistor comprising:forming a field termination junction around the perimeter of asemiconductor substrate; forming an epitaxial layer on the semiconductorsubstrate; patterning and etching a plurality of trenches into theepitaxial layer; depositing polysilicon to fill the trenches; doping thepolysilicon with a dopant of a first type; patterning the substrate andimplanting a dopant of a second, opposite type to form a plurality ofwells interposed between adjacent trenches; patterning the substrate andimplanting a dopant of the second type to form a plurality of seconddopant type contact areas and a plurality of heavy bodies positionedabove the wells, each heavy body having an abrupt junction with thecorresponding well; patterning the substrate and implanting a dopant ofthe first type to provide source regions and first dopant type contactareas; and applying a dielectric to the surface of the semiconductorsubstrate and patterning the dielectric to expose electrical contactareas.
 37. The method of manufacturing a trenched field effecttransistor of claim 36, wherein the trenches are patterned to extend inone direction and be substantially parallel to each other.
 38. Themethod of manufacturing a trenched field effect transistor of claim 36,wherein the patterning and implanting steps further comprise arrangingthe first dopant type contact areas and second dopant type contact areasin alternation and extend linearly between adjacent trenches.
 39. Themethod of manufacturing a trenched field effect transistor of claim 36,wherein the implanting step for forming the heavy bodies comprisesimplanting a first dopant at a first energy and dosage and a seconddopant at a second energy and dosage, the second energy and dosage beingrelatively less than the first energy and dosage.
 40. The method ofmanufacturing a trenched field effect transistor of claim 36, whereinthe implanting step for forming the source regions comprises implantinga first dopant at a first energy and dosage and a second dopant at asecond energy and dosage, the second energy and dosage being relativelyless than the first energy and dosage.
 41. The method of manufacturing atrenched field effect transistor of claim 36, wherein the heavy bodiesare formed prior to forming the source regions.
 42. The method ofmanufacturing a trenched field effect transistor of claim 36 wherein thesource regions are formed prior to the heavy bodies.
 43. The method ofmanufacturing a trenched field effect transistor of claim 36 whereinsaid field termination is formed by forming a trench ring.
 44. Themethod of manufacturing a trenched field effect transistor of claim 36wherein said field termination is formed by forming a deep well dopedwith a dopant of the second dopant type.
 45. The method of manufacturinga trenched field effect transistor of claim 36 wherein said dielectricis applied before the steps of forming the heavy bodies and seconddopant type contacts, and the dielectric provides a mask for thepatterning of the heavy bodies and second dopant type contacts.